Structures and Methods for Wafer Packages, and Probes

ABSTRACT

This document describes the fabrication and use of multilayer ceramic substrates, having one or more levels of internal thick film metal conductor patterns, wherein any or all of the metal vias intersecting one or both of the major surface planes of the substrates, extend out of the surface to be used for making flexible, temporary or permanent interconnections, to terminals of an electronic component. Such structures are useful for wafer probing, and for packaging, of semiconductor devices. In some embodiments, such structures are shown to be useful for simultaneously testing multiple devices on a semiconductor wafer, or for assembling multiple substrates on to a wafer, to accomplish both testing and packaging of the dies on the wafer. In yet another embodiment of the invention, single or multilevel ceramic interconnect structures with thick film metal conductors, are fabricated right on the product wafer to facilitate economical testing and packaging of the dies on the wafer.

The present application claims priority from the provisional patentapplication, serial number 61/096,315, filed on Sep. 12, 2008, titled“Structures and Methods for Wafer Packages, and Probes”, herebyincorporated by reference.

BACKGROUND

The semiconductor technology has been following Moore's' lawrelentlessly over the past two decades, with device densities nowcontaining several million transistors. This has translated into everincreasing challenges in testing and packaging of these devices due togreatly increased need for input/output (I/O) terminal pads anddecreased pad size and spacing. The leading-edge pad pitches and sizesare under 50 μm, a limiting value for wirebond technology. This hashastened the migration to area array solder bump, or flip chip bonding,which accommodates increased number I/O pads, significantly relaxing thepad size and density constraints for many memory devices. For ASICs andmicroprocessor type devices, number of area array I/Os numbers, haveroutinely exceeded a thousand pads on a single device or chip, requiringever smaller pad sizes and pitches, currently reaching 75 μm pads on 150μm, respectively. The area array technology brings its own uniquechallenges in processing, package reliability, and testing. Added tothese are the challenges to reduce the costs in device fabrication,testing, and packaging.

These challenges have been met though technological innovations intesting and packaging, materials, and structures. For packaging, theindustry has developed low cost flip chip bonding substrates shown inFIG. 1.

Flip chip solder interconnection, also called Controlled Collapse ChipConnection or C4, for short, was first introduced by IBM more than 30years ago. Kumar et. al. (U.S. Pat. No. 4,301,324) developed ceramicsubstrates of nearly same coefficient of thermal expansion, (CTE), asthe device chip, allowing for very highly reliable solder connections.Today's lower cost flip chip packages are made from plastic packageswith high Coefficient of Thermal Expansion (CTE). In recent years therest of the industry has also widely adopted this method ofinterconnection for connecting the chip directly to the board, invitingserious reliability problems involving fatigue failures in the solderjoints. Adoption of flip chip, area array terminals for even low I/Odevices has enabled packaging these devices on the wafer itself,thorough the so called Wafer Level Packaging, (WLP), methods, greatlyreducing cost.

Reliability of flip chip solder joints to second level packages such asprinted wiring boards, (PWB), is a serious concern, and becoming more soas the pad sizes decrease. One widely adopted mitigation strategy toenhance solder joint reliability is to use a polymer fill under the chip(so called ‘underfill), entailing extra costs for process, materials,equipment, and yield loss. Another strategy, just coming into use,particularly for microprocessor device chips, is the so-called ‘copperbumps’, once again adding cost and complexity. This concern seriouslyjeopardizes the migration to smaller pad sizes pitches projected by theindustry. While they add much cost and process complexity, thesemeasures only improve fatigue life by less than a third.

Industry has also developed a versatile vertical probe technology usingdiscrete metal wires, so-called COBRA probes, to test these area arraychips. The increased numbers, densities, decreased sizes of area-arraypads on device chip have brought about a commensurate need for newvertical probe technologies. Available vertical probe technologies arecomplex, expensive, and delicate. The introduction of micro-fabricatedcantilever probes has met the challenges in testing the closely spaced,smaller wirebond pads. The so-called multi-DUT probes constructed fromthese have enabled greatly increased productivity though their abilityto contact many dies simultaneously i.e. increased ‘test parallelism’.

One common method to form arrays of vertical probes is to attach metalwire extensions to the co-planar pads on the surface of substrates, sameones used for packaging the dies. The wire extensions are essentiallytruncated gold wire bonds formed on the gold plated substrate pads. Thepackage provides the necessary electrical connections to the ‘wireprobes’, routing them to conveniently spaced and located interconnectionterminal pads used to join to the next level of interconnection, such asa printed wiring board, (PWB). This routing can be either to padslocated on the same side of the central probe array, i.e. co-planarrouting or, as is more common, to the opposite surface of the surface ofthe package. In this context, the package is often referred to as the‘space transformer’ because, invariably, the pad spacing of the terminalpads are much wider than that of the probe array. In this document theterms substrates and space transformers are used interchangeably. Thespace transformers are generally made of ceramic packages, oftenmulti-layer ceramic packages with several levels of internal wiring,terminating on both the probe side and the ‘board side’, in co-planarpads that may be plated with nickel and gold. To form the probe array,soft gold wires are ultrasonically bonded to the pads, and speciallyshaped before truncating and planarizing the tops. The soft gold wiresmay be stiffened by coating with polymer, or with nickel alloys. Specialtips and ‘electro-formed’ arrays of cantilever beams of a suitable metalalloy are attached to the ends of the probes from wafer templates. Yetanother method for forming probes involves building probe arrays onspace transformers by lithographically patterned and plated thin films.Here, multiple plating steps are needed to obtain probe structuressufficiently tall, often as much as 0.5 to 2 mm, to overcome the globaland local positional variations in the locations of the test pads on thewafers. Such micro-fabrication methods, can be carried out either righton the space transformer, or fabricated separately and transferred tothe space transformer. The wire-bond probes and the micro fabricatedprobes are both delicate structures, which when bent or broken, are hardto repair or replace. Invariably, the probe cross-sections in thesestructures are significantly smaller than the diameters of the pads onthe space transformer to which they are joined. Also they are adhered tothe pads of the space transformer over-plating a hard metal on the baseor joined with solder or braze. For these reasons, multi-Device UnderTest (DUT) probes are fragile and, expensive.

In the prior art wafer probe structures discussed above, the processcomplexities, and the high fabrication costs, are the direct result ofthe need to elevate the probe tips significantly above the surface ofthe space transformer. This, in turn, is dictated by the requirement forthe probe tips to bend and conform to the thousands of test pads on awafer, compensating for the expected variations in probe heights, i.e.planarity, and variations in the wafer thickness, in pad sizes,locations, together adding up to 100-500 microns. Depending on the sizeof the probe array, the probe heights required to compensate for thesefactors can range from 25 μm, for a single DUT, area-array probe, to 500μm for a multi-DUT probe. Some bending or compliance of the probe isalso required to provide a level of ‘scrub’ needed to break though oxideformed on the wafer terminals. Sophisticated probe array positioning andtilting schemes can decrease these heights, somewhat.

SUMMARY

The present invention relates generally to methods and apparatuses forsemiconductor chip packaging and testing, such as ceramic packages orceramic probes for device testing. In an embodiment, the presentinvention discloses a contactor for semiconductor chips, and methods forfabricating the contactor. The present contactor comprises a pluralityof via extensions, protruding from the top and bottom surfaces of thecontactor. The via extensions have aspect ratio higher than 2×1, forexample, to compensate for the height mis-matched between viaextensions. In an aspect, the diameter of the via extensions is lessthan 500 microns, and preferably less than 100 microns. These viaextensions are designed to be bonded to the bond pads of thesemiconductor chips, for example, by soldering. Thus the size of the viaextensions is preferably less than the bond pads' dimension. Solderingprovides a potential alignment between the via extensions on thecontactor and the bond pads on the semiconductor chips.

In an embodiment, the present contactor comprises a plurality of viaextensions having contact tips fabricated from a semiconductor wafer. Byfabricating the contact tips on a semiconductor wafer, the viaextensions of the contactor can have the accuracy of semiconductorprocessing and the planarity of semiconductor wafer. The bonding betweenthe via extensions and the contact tips can be accomplished bysoldering, which can accommodate minor mis-alignment. In an aspect, areleasable layer is coated on a semiconductor wafer before the contacttips are formed, for example, by patterning and depositing. Afterbonding the via extensions to the contact tips, the releasable layer isreleased, freeing the contact tips from the semiconductor wafer.

In an embodiment, the present contactor comprises a plurality of viaextensions having constricted solder bridge to allow ease of rework. Theconstricted solder bridge limits the amount of solder between the viaextensions and the bond pads, thus providing a solid electricalconnection between the contactor and the chip, and at the same time,providing a minimum soldering required to allow ease of removal. In anaspect, the constricted solder bridge comprises a coating, e.g., apolyimide coating, on the surrounding sides of the via extensions,preventing soldering to be attached to these sides. Thus the solder onlyattaches to the tip of the via extensions, or a portion of the topsurface of the via extensions. In this case, after re-heating, thecontactor and the chip can be separate with relative ease.

In an embodiment, the present invention discloses a chip packagecomprising a contactor having a plurality of via extensions solderinglybonded to the bond pads of one or more semiconductor chips. The use ofsoldering bonding allows the compensation for minor mis-alignment, bothin lateral dimensions and in vertical dimension.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates prior art chip bonding.

FIG. 2 illustrates an exemplary chip size package to make permanent ortemporary interconnections to devices with solder terminals.

FIG. 3 illustrates an exemplary LTCC process flow.

FIG. 4 illustrates an exemplary process of forming packages with viaextensions.

FIG. 5 illustrates an exemplary full wafer flip chip, assembled onmonolithic full wafer stud substrate.

FIG. 6 illustrates an exemplary wafer-level assembly of chip studpackage.

FIG. 7 illustrates an exemplary self-aligning flip-chip attached towafer template, followed by wafer removal.

FIG. 8A illustrates an assembled probe package.

FIG. 8B illustrates a prior art probe assembly.

FIG. 9 illustrates an exemplary process of forming studs with co-firedtips

FIG. 10 illustrates a ceramic space transformer formed in-situ on aproduct wafer by aligning, attaching, and firing on a wafer size greenlaminate. The devices on the wafer can be tested at wafer level, ordiced into die-sized packages for testing.

FIGS. 11 and 12 illustrate an exemplary process flow for forming acontactor according to embodiments of the present invention.

FIGS. 13 and 14 illustrate an exemplary process flow for forming acontactor with contact tips fabricated from a semiconductor wafer.

FIGS. 15 and 16 illustrate an exemplary process flow for forming acontactor with constricted solder bridge.

FIGS. 17A-17C illustrate an exemplary rework process for bonding acontactor with constricted solder bridge to a temporary substrate.

FIG. 18 illustrates an exemplary bonding for un-constricted viaextensions.

FIG. 19 illustrates an exemplary embodiment of the present integratedcontactor on semiconductor wafer.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

This invention in several of its embodiments addresses the twinchallenges posed by today's high density flip chip devices, viz. needfor, (1) packaging technology that provides highly reliable solderjoints in flip chip device packaging, and, (2).vertical probe arraysthat are rugged, inexpensive, simple, and scalable. The common elementfor achieving these goals is a multilayer ceramic (MLC) substrate,having a coefficient of thermal expansion, CTE well matched to that ofsilicon, and having co-formed via extensions, or via studs illustratedin FIG. 2. The methods for fabricating these CTE-matched substrates alsolends itself to fabricating them on product wafers, to obtaining greatbenefits to semiconductor manufacturers in wafer-level testing, burnin,and packaging.

In prior art, such co-formed or co-fired metal studs have been use, inone instance (D. Boss, A. Kumar et.al., U.S. Pat. No. 4,880,684), totranslate the thin-film metal pads of the substrate thorough a softpolymer layer, upon which thin film pads are formed. The soft polymerlayer shields the weak ceramic from cracking, due to the combinedstresses of the thin film pad, and the solder joint to the chipterminals that sits on the pads. This entails high costs associated withcoating a thick polymer layer over the studs, planarizing to expose thetops of the studs and thin film deposition and patterning of theterminal pads for solder attachment .

In another instance, (Itakagi, et.al. Intl. J. Microelectronics, pp.46-51, 1997) similarly co-formed studs are used to make permanent, lowstress, direct electrical connection to I/O pads of the chip, using softconductive adhesives. The via studs are short, and the CTE of thesubstrate is not required to be matched to that of silicon. Suchconductive adhesives have poor electrical conductivity, high contactresistance, and are not reliable in long term usage. Also, flip-chipconductive adhesive joining, unlike flip-chip solder joining, lacks theability for self-alignment, necessitating precise die placement duringjoining. The structure of this prior art also requires additionalreinforcement of the conductive adhesive joints in the form of a resinunderfill layer, further adding cost and complexity.

The structures and methods of this invention are aimed at avoiding thecomplexity, cost, performance and reliability issues with conformed viastud structures, and of their use, in the above cited prior art methods.These via studs are merely extensions of thick film copper or silvervias from one or more layers of the substrate and are connected toInput/ output (I/O), pads on the other side by redistribution lines. Thevia studs of this invention can be used for forming dense arrays of,flexible, low stress interconnections to silicon devices by flip chipsoldering. The flexibility of the studs and the silicon CTE-matchedceramic in which they are rooted, make it possible to have highreliability, flip-chip solder interconnections.

These via studs, or hereinafter referred to simply also as studs, canalso be used as flexible, elongated probes in wafer probing. Byco-forming the studs during the substrate fabrication, the extra expenseof wire attach, or micro-fabrication methods used for forming suchelevations, are avoided here. The studs can be made sufficiently long,ranging from 25 μm to 1000 μm, longer if needed, to provide thenecessary elevation to the probe tips to satisfy the planarity andcompliance required for probe arrays to simultaneously contact all thetest pads across a multiplicity of devices, across the whole wafer. Thepreferred range of the heights of the studs is from 50 μm to 250 μm.These studs, which are of the same diameter as the buried vias, will bequite rugged unlike the wire-bond formed probes of prior art. The probesof prior art, which are joined to the corresponding pads of the spacetransformer by weak gold-to-gold bonding, and require reinforcing in theform of over-plating, or solder coating the bond area. In contrast, thestud probes of this invention will be well anchored to the vias withinthe ceramic.

In the wafer probe application, these studs can be provided with specialmetal tips, using a silicon wafer as the template for the test pad tips,by flip-chip solder method that will naturally assure a high degree ofco-planarity, and lateral positional accuracy for the probe tips. Herethe self-aligning ability of flip chip solder interconnections is usedto achieve this.

Other embodiments of this invention provides method for fabrication ofthese space transformers, and methods for using these for eithertesting, packaging, or for both. Such space transformers are also usefulfor diced single device chips, or for wafer-level testing and assembly.

Fabrication of Ceramic Substrates with Via-Studs:

Multilayer ceramic, (MLC), substrates have been in use for packagingsingle, and multiple chips for sometime. The most common method fortheir fabrication uses ‘green tapes’ for forming ceramic layers andthick film inks or pastes for forming conducting patterns in the layers,and layer-to-layer interconnections, commonly referred to as vias. The‘green tape’ is made by casting a paint-like slurry containing powdersof a suitable ceramic and glass, with a polymeric binder dissolved inorganic solvents, on a polymer film such as Mylar™ by the so calleddoctor blade method. Examples of polymeric binders are butadiene, orButvar™, Poly-methyl methacrylate (PMMA). Mixtures of alcohols, such asIsopropyl alcohol, (IPA), and methanol, or ketones such as methyliso-butyl-ketones (MIBK) are common solvents and vehicles for theslurry. After the solvents evaporate, the , the paper thin and, rubberygreen tape, now consisting ceramic and glass particles in a matrix ofthe polymeric binder, is cut or ‘blanked’ to size with alignment holesat the corners. Via holes are punched at the required locations byautomated mechanical methods using a programmable die and punch set, orby laser drilling. The conductor patterns are printed on to the greentape layers, using screens or stencils cut in metal foil, and the viaholes are also filled with the same or similar conductor inks The greentape layers are stacked in the required order and in good alignmentbetween the layers, and laminated at a temperature of about 100° C., andpressures of between 250-1000 psi. in a laminating press, to obtain amonolithic ‘green laminate’. The green laminate is then ‘sintered’ by aprogrammed heating regimen, in suitable furnace ambient, first tocompletely remove the polymeric binder, and subsequently to sinter theceramic powder, the metal particles in the conductor lines and vias, toobtain a monolithic sintered ceramic substrate with interconnected,buried and surface conductor patterns.

Commonly used ceramic powder in multilayer substrates is alumina, whichwould constitute from 80-96% by weight in the green tape with certainalkaline earth alumino-silicate glasses the remainder. When alumina isused as the ceramic, its high sintering temperatures requires the use ofmolybdenum or tungsten inks to form the conductors. The steps involvedin the fabrication of such multilayer substrates are shown in FIG. 3. Agood description of such multilayer substrates, including a detaileddescription of the steps in their fabrication, is given by in‘Microelectronic Packaging” by A. R. Blodgett & D. R. Barbour,Scientific American, V 249 (1), pp 86-96 (1983). Because of the hightemperatures (>1400° C.) involved in the fabrication, this technology iscommonly referred to as High Temperature Co-fired Ceramic, (HTTC)technology.

Certain special glass compositions whose powders sinter well between800° C.-1000° C., while simultaneously becoming crystalline, are usefulin fabricating a lower temperature version of this technology in orderto enable the incorporation highly conductive thick film metallurgy ofcopper, silver, or gold. Compositions consisting of physical mixtures ofceramic powders, usually alumina, with significant volume fraction ofglasses that soften and flow at temperatures well below 1000° C. arealso used for fabricating such multilayer structures. This technologyfor fabricating multilayer structures at these relatively lowertemperatures to be compatible with thick film inks of silver, copper orgold, is commonly referred to as Low Temperature Co-fired Ceramic (LTCC)technology.

The total shrinkage of the green laminate on the way to fulldensification is about 50% by volume. In the prior art, a method forsintering LTCC substrates that completely suppresses the lateral (x, y)shrinkage of the substrates, forcing the entire shrinkage of the greenlaminate to take place in the Z- or thickness direction, involves usinga green tape layer consisting of a refractory ceramic such as alumina,that is co-laminated to the top and bottom of the LTCC green laminate.We shall refer to the green tape layer containing the inert ceramicpowder as the ‘contact sheet’. During sintering of the LTCC substrate,in the temperature range of 800° C.-1000° C., the ceramic powder in thetopmost and bottommost contact sheet layers, does not densify and,thereby, prevents the lateral shrinkage of LTTC layers in between. This,in turn, forces the LTCC layers to densify totally in the z, orthickness direction. After the substrate is fully sintered and cooled,the inert contact layers, now reduced to a loose agglomeration of theinert ceramic powder, can be easily removed with a jet of water or airand the LTCC substrate is finished with plating or other operations foruse as packages for semiconductor devices.

The via extensions are formed as follows: the inert contact layer forthe top side is provided with the same filled via pattern as the topmostLTCC green tape layer, and co-laminated top most LTCC layer along withthe rest of the green laminate. After the LTCC substrate is fullysintered, the inert ceramic layers are removed by blowing off with a jetof air or of water. This exposes the ‘via-extensions’ or ‘studs’attached firmly to the vias emerging from topmost layer of the LTCCsubstrate. The height of the stud will generally end up to be about 50%of the thickness of the contact sheet in the green state, whichtypically ranges from 50 μm to 250 μm. The resulting metal studs willhave a uniform height, which can range from 25 μm to 125 μm, dependingon the thickness of the green sheet used for the contact layer. Toobtain even taller studs, more than one green tape contact sheets withpaste-filled vias, are co-laminated to the LTCC layers tape layers.Staggered stud structures can be obtained by slightly displacing thevias in the contact sheets to a little extent. Even cantileverstructures can be produced by using multiple contact sheet layers andprinting the cantilever part of the structure on its surface andconnected to the stud via. After the substrates are sintered the ceramicpowder of the contact layer is washed off or blown-off without damagingthe studs standing proud of the LTCC surface.

The same can be done to the bottom contact sheet of the green laminateto obtain via extensions there as well (FIG. 4). The inert contact sheetlayers on the opposite side can also be utilized as above for formingstuds. Generally the numbers of I/Os needed on the ‘board side’ aresignificantly smaller than on the device side, thereby allowing forlonger and larger diameter studs to be provided on this side. Thesestuds would allow for easy electrical contact for testing and burn-inand very reliable permanent terminal for board attachment with reflowsoldering methods. In all the application examples to follow, thebackside studs are shown, but it should be understood that other formsof backside terminals such as thick film or thin film metal pads, ballgrid arrays, soldered or brazed pins, etc. are equally applicable. Inthe description of our invention that follows, we will interchangeablyuse substrates with studs on one side (device-side only) or on both,device side and the printed wiring board (PWB), or simply ‘board side’.

Using these methods, the substrate with via studs can be fabricated fordevice packaging. A wide choice of LTCC compositions are availablecommercially-available for fabrication of the LTCC substrates of thisinvention. In our preferred approach, a MgO-Al2O3_SiO2 glasscomposition, having MgO in the range of 15-28% by weight, Al2O3 in therange of 9-15% by weight, the remainder being silica, except for lessthan 2% of nucleating agents such as TiO2, ZrO2, P2O5, or B2O3. Theglass powder of this composition fully densifies and crystallizes in thetemperature range of 850 C to 950 C, thereby co-sintering with thickfilm silver or copper pastes. Furthermore, the resulting ceramic has adielectric constant of about 5, which is very good for packagingapplication. It has the additional benefit of having thermal expansioncoefficient closely matched to that of silicon.

Monolithic Substrate for Packaging and Probing:

Space transformers with studs can be made either in a multi-up ormultichip configuration. Multichip packages, can have shared circuitry,and are used as such for mounting several different types of chips toobtain a subsystem. In the multi-up configuration, a contiguous array ofchip size space transformers having the same size and positionalrelationships as the devices on the corresponding product wafer, areformed for possible use as a wafer-scale contactor. Such a multi-upspace transformer can also be diced to many chip-size spacetransformers, to be later re-assembled into multi-Device Under Test,multi-DUT, contactors, as described later. Each transformer in amulti-DUT space transformer is a distinct unit with no shared circuitry.Multi-up substrates form the basis for the embodiments of thisinvention.

When the entire wafer is permanently assembled to the wafer-sizedmonolithic substrate as shown in FIG. 5, the I/O pads on the oppositeside of the substrate, which are less numerous, larger, and much morewidely spaced, can be accessed for electrical testing, and even burn-in.It is obvious, that such a scheme for permanently attaching an entiredevice wafer to a substrate can only be useful when the devicetechnology is stable, and device yields are high, and there is room forsignificant redundancies in the number of devices good when needed inthe application. For full wafer flip chip process, the whole wafer isassembled on monolithic full wafer stud substrate, with the packageoutline fitting within the dicing lanes on the wafer.

When a substrate with studs is permanently attached to a semiconductordevice for packaging by a flip chip solder method, the elongated studsprovide considerable mechanical flexibility to the interconnection, andthereby help to enhance its fatigue life. This is analogous to theso-called copper bump technology that has been introduced by leadingsemiconductor makers to accomplish the same, at considerably lower costthan the latter.

The monolithic wafer- size, multi-up substrate assembly shown in FIG. 5,can also be used solely for performing wafer-scale testing, and burn-in,if the solder attachment can be designed to be easily re-workable. Oneway to enable this is to limit the attachment area of the solder on topof the I/O studs on the package. A method for restricting the solderattach area is to place a polymer sheet with small holes drilled in itthat correspond accurately to the I/O layouts of the devices across theentire wafer. The size of these holes are made to be just large enoughto allow for easy solder penetration and coalescence of molten solderfrom both sides and, yet be small enough to easily and predictablyseparate the wafer from the package without significantly changing thesolder balls on either. High temperature polyimide is an appropriatematerial for separation sheet in this use.

The probe assembly of FIG. 5 can also be used to make electricalconnection to the test pads on a wafer though compliant z-axisconnectors. Here, the normally non-conductive connector sheet willbecome locally conductive at points where the probes press on it againstthe wafer. Many other types of commercially available z-axis conductorscan be used in the place of the Fujitsu material cited as an exampleabove.

The monolithic wafer-scale-package with studs of FIG. 5 can also be usedsolely as a monolithic wafer-scale contactor for directly contacting thedevice terminals on the product wafer. Here the studs are brought onlyinto physical contact with the terminals on the wafer, in a ‘wafertester’.

Assembled Packages and Probe:

Another way to accomplish the wafer level assembly for testing, burn-inand packaging, is to attach individual device-size space transformers ofthis invention, on to wafer by flip chip methods. The packages should besmall enough to fit well within the dicing lines on the wafer. Theself-aligning ability of such flip chip attachment enables accurateplacement and assembly by using screen printed solder and metal stencilsfor packages to be dropped in, and reflow bonding of the packages overthe entire wafer. When thus joined, the I/O terminals of the packages onthe board side can be easily accessed for device testing and burnin,prior to dicing the packaged devices. Here, the individual device-sizepackages are tested, burnt-in, diced and shipped, as packaged dies. Sucha packaging and assembly scheme is illustrated in FIG. 6.

In a preferred method for forming an assembled wafer-scale-contactor,the single-chip size stud substrates are carefully assembled to obtain amulti-DUT wafer probe, using a wafer template having metal terminalsidentical to those on the product wafer, on a sacrificial metal layer.The terminal pads on the wafer template are fabricated on a sacrificialmetal layer of aluminum. The wafer terminal pads will be at theircorrect nominal locations. However, the tips of the stud may bedisplaced from their correct lateral positions by small amounts. Here,the well known self-aligning characteristic of the flip-chip solderbonding comes to play and corrects small variations in x-y and zpositional locations of the studs. The solder columns distort in shapeto reach terminal pads on the wafer from slightly misaligned studs, asillustrated in FIG. 7. The planarity of the chip terminal pads isassured by holding the wafer flat against a flat wafer chuck duringsolder reflow. After such assembly, the space transformer array iscaptured by potting in suitable material, such as epoxy, before beingreleased from the template by dissolving the sacrificial metal layer.Such an assembled multi-DUT probe is illustrated in FIG. 8A. Also shownfor comparison in FIG. 8B is a prior art multi-DUT probe assembly,assembled using many individual single-chip ceramic packages, eachsmaller than the size of the devices, where the coplanar thin film metalpads, typically 10 μm or less in height, are used as the contactingprobes. To achieve reliable contacting of the device test pads, thesethin film pads should have extra-ordinary co-planarity. To achieve this,the single-chip packages are painstakingly assembled on to a speciallyconstructed mechanical support and potted in place with a pottingcompound. The other shortcoming is the reliance on purely mechanicalmeans to assure ‘probe’ planarity.

The fabrication of LTCC substrates with integral via studs, describedpreviously, can also be extended to provide, co-fired, sintered tips,with the required positional accuracy, together with required tip shapesas follows. The green LTCC laminate with the top bottom inert contactlayers containing vias filled with metal pastes that form the studs, areusually fired on ceramic setter tiles. Here, in this embodiment, thesetter tile is replaced by a silicon wafer template provided with shapeddimple arrays at locations corresponding to the terminals of the devicewafer to be tested. These dimples are filled with suitable metal paste,the same one used to form the stud, i.e. copper, silver, or gold. Nextthe green (i.e. unfired) LTCC laminate, with contact layer, is placed ingood alignment between the stud locations and these tip arrays on thewafer template, using an alignment aligning fixture. The green laminateis then sintered, as usual, to densify the LTCC ceramic and the metalinterconnects. During sintering, lateral shrinkage of the laminate iscompletely suppressed, and the entire densification is accommodated bythe shrinkage in the thickness direction. During this process, thepaste-filled dimples in the silicon wafer template also densify to formshaped tips, and attach themselves to ends of the studs in the inerttape layers. The sintered laminate is released, and the inert ceramicpowders of the contact layers are removed by washing or blowing off.Since the wafer template does not shrink laterally during sintering, thelocations of the tips are fixed. Also the flat wafer template assuresboth positional accuracy and co-planarity of the tips. The methods toform accurately shaped and sized dimples in the wafer template is byanisotropic etching though a resist pattern is well known in the art.This typically produces pyramid-shaped tips (FIG. 9).

FIG. 10 illustrates a further embodiment of this invention. Here, thewafer template of the above example is replaced by a un-processed wafer,i.e. one without devices fabricated thereon. Here the un-processedproduct wafer is first provided with though-silicon-via holes to enablelater electrical connection to device terminals to be fabricatedsubsequently on the wafer-side of ceramic-wafer composite. The greenceramic laminate with thick film silver metallization paste circuitpattern throughout, including silver paste-filled vias on both sides isprepared with a co-laminated contact sheet on the ‘board-side’ only, isalso prepared separately. The green laminate thus prepared is placed onthe previously prepared un-processed wafer such that the vias filledwith silver paste on the ‘device side’ of the laminate are in goodalignment with the corresponding though-silicon via holes, and pressedthereon at moderate temperature and pressure. The wafer-laminateassembly is then cured at the required high temperature to consolidatethe ceramic dielectric and the silver conductor features. The contactsheet on one side and the solid wafer on the other, act to eliminate anylateral shrinkage in relatively thin laminates, thus preserving thelocation accuracy of the circuit features. During this consolidation,the ceramic dielectric strongly bonds to the oxidized surface of thesilicon wafer forming in-effect, a silicon-on-insulator or SOI waferwith built-in through-silicon-via holes, and an integral ceramicinterconnect structure. The SOI wafer is then used to fabricate desiredsemiconductor devices thereon, including through-silicon-viainterconnections, to the silver pads on the integral package, by methodsknown to the industry. This scheme will provide a very economical meansfor wafer-level testing and packaging. To successfully accomplish thisin-situ substrate fabrication, the starting glass in ceramic compositionshould densify and adhere well to the oxidized silicon surface, andposses a coefficient of thermal expansion well matched to that ofsilicon. MgO—Al₂O₃—SiO₂ glasses cited earlier, have these attributesThis also accomplishes several major objectives of Intel Corporation'sso-called, “Bumpless Bonding Build-Up Laminate (BBUL”) structure (Towleand Wermer, U.S. Pat. No. 6,555,906), on a wafer-level, elegantly andeconomically.

FIGS. 11 and 12 illustrate an exemplary process flow for forming acontactor according to embodiments of the present invention. Operation100 forms a plurality of insulating layers having embedded interconnectsand vias (FIG. 12A). The insulating layers 110 can be ceramic greensheets, with conductive lines 112 for interconnects, and filled punchedholes 111 for vias. Operation 101 laminates the plurality of insulatinglayers together with proper alignment (FIG. 12B). Operation 102laminates a contact layer on top and a contact layer on the bottom ofthe plurality of insulating layers (FIG. 12C). At least one contactlayer 113 or 114 has embedded via extension patterns 115, which arefilled with conductive material and have aspect ratio higher than 2×1.The high aspect ratio can be accomplished with small via size toaccommodate the bond pads of the chip. Operation 103 cures the layers ata predetermined temperature. The insulating layers are solidified withcertain degrees of shrinkage. The contact layers does not shrink, butconverted to powder. Operation 104 removes the powdered contact layers,exposing the via extensions (FIG. 12D).

FIGS. 13 and 14 illustrate an exemplary process flow for forming acontactor with contact tips fabricated from a semiconductor wafer.Operations 120-124 form the contactor with exposed via extension,wherein the contactor can have one or two contact layers with filled viaextensions 115 (FIG. 14A). The aspect ratio of the filled via extensionsis preferably higher than 2×1, but in general can be any value.Operation 125 forms contact tips on a semiconductor wafer 132 withsimilar via extension patterns 131 (FIG. 14B). The planarity of thecontact tips is thus determined by the flatness of the semiconductorwafer, allowing an accuracy in planarity of the contactor suitable forsemiconductor device testing. The process of the contact tips can beperformed by semiconductor processing, thus provides lateral dimensions,and lateral accuracy, of semiconductor processing, similar to that ofthe bond pads of semiconductor devices. Operation 126 bonds the viaexensions 115 to the contact tips 131 (FIG. 14C). The bonding can beperformed by soldering, with potential mis-alignment correction asdiscussed above. Operation 127 removes the semiconductor wafer from thecontactor, forming a contactor having contact tips with planarity andlateral accuracy of semiconductor processing (FIG. 14D), suitable formatching the bond pads of semiconductor devices in testing.

FIGS. 15 and 16 illustrate an exemplary process flow for forming acontactor with constricted solder bridge. Operations 140-144 form thecontactor with exposed via extension, wherein the contactor can have oneor two contact layers with filled via extensions 115 (FIG. 16A). Theaspect ratio of the filled via extensions is preferably higher than 2×1,but in general can be any value. Operation 145 forms a constrictedsolder bridge 191 on the via extension 115 (FIG. 16B). In an aspect, theconstricted solder bridge 191 limits the soldering surface of the viaextension 115, for example, protecting the side surfaces from beingsoldering, and allowing only the top surface 192 to be soldered.

FIGS. 17A-17C illustrate an exemplary rework process for bonding acontactor with constricted solder bridge to a temporary substrate. Thesubstrate 200 (for example, a semiconductor chip) has bond pads 202 foraccessing internal devices. A contactor is bonded to the bond pads withsolder 203 bonding with the constricted solder bridge. After finishtesting the chip, the contactor is removed. Under heated environment,such as heating the contactor, the solder is reflow and the contactorcan be pulling out of the chip. Since the bonding between the viaextensions and the bond pads is restricted, the solder 204 can be brokenoff, and separated into residues 205.

FIG. 18 illustrates an exemplary bonding for un-constricted viaextensions. Without the constricted solder bridge, the solder can bond213 to the top and side surfaces of the via extensions, forming apermanent bonding between the bond pads 202 of the chip 200 with thecontactor.

FIG. 19 illustrates an exemplary embodiment of the present integratedcontactor on semiconductor wafer. Operation 220 prepares a semiconductorwafer, for example, with devices and interconnections. Operation 221forms a plurality of insulating layers with embedded interconnects andvias. Operation 222 laminates a plurality of insulating layers on thedevice wafer, and operation 223 cures the laminated layers and the waferat a predetermined temperature. This process forms an integrated waferpackage, complete with a contactor on a semiconductor wafer. The wafercan then be tested and/or diced into individual chips.

1. A contactor comprising: an insulating substrate having a top surfaceand a bottom surface; a plurality of conductive top via extensions, thetop via extensions protruded partially above the top surface with higherthan 2×1 aspect ratio; a plurality of conductive bottom via extensions,the bottom via extensions protruded partially above the bottom surfacewith higher than 2×1 aspect ratio; one or more layers of interconnectslocated within the insulating substrate, each interconnect connecting anumber of via extensions.
 2. A contactor as in claim 1 wherein theprotruding via extensions are embedded partially in the insulatingsubstrate.
 3. A contactor as in claim 1 further comprising: a pluralityof conductive vias, the vias totally embedded within the insulatingsubstrate and connecting the interconnects between the layers.
 4. Acontactor as in claim 1 wherein the number of via extensions is morethan the number of bottom via extensions.
 5. A contactor as in claim 1wherein the insulating substrate is a ceramic substrate.
 6. A contactoras in claim 1 wherein the via extension protrudes less than 1 mm fromthe top surface.
 7. A contactor as in claim 1 wherein the via extensionsare having a uniform height.
 8. A contactor as in claim 1 wherein thevia extensions are straight, staggered or having a cantilevel structure.9. A contactor as in claim 1 wherein the insulating substrate has athermal coefficient similar to that of silicon.
 10. A contactor as inclaim 1 wherein the insulating substrate comprising a composition ofMgO, Al₂O₃, and SiO₂.
 11. A contactor as in claim 1 wherein the viaextensions are coated with a solder material, or presenting a solderableconductive surface.
 12. A contactor comprising: an insulating substratehaving a top surface; a plurality of top conductive via extensions, thevia extensions protruded partially above the top surface; one or morelayers of interconnects located within the insulating substrate, eachinterconnect connecting a number of via extensions; a plurality ofcontact tips disposed on top of the via extensions, the contact tipshaving the planarity and the spacing accuracy of semiconductorprocessing, wherein the contact tips bonded to the via extensions bysoldering.
 13. A contactor as in claim 12 wherein the tips arefabricated separately on a semiconductor substrate before attaching tothe via extensions.
 14. A contactor comprising: an insulating substratehaving a top surface; a plurality of top conductive via extensions, thevia extensions protruded partially above the top surface; one or morelayers of interconnects located within the insulating substrate, eachinterconnect connecting a number of via extensions, wherein the viaextensions comprise a constricted solder bridge to allow ease of rework.15. A contactor as in claim 14 wherein the via extensions comprise aninsulating coating with opening on top.
 16. A contactor as in claim 14wherein the via extensions have a portion of the side surface near thetop surface of the insulating substrate protected from being soldered.17. A contactor as in claim 14 wherein the via extensions have apolyimide coating on a portion of the side surface near the top surfaceof the insulating substrate.
 18. A contactor as in claim 14 wherein thevia extensions have the top surface solderable or coated with solder.19. A chip package comprising: a contactor comprising an insulatingsubstrate having a top surface; a plurality of conductive viaextensions, the via extensions protruded partially above the topsurface; and one or more layers of interconnects located within theinsulating substrate, each interconnect connecting a number of viaextensions; a semiconductor chip having a top surface with a pluralityof interconnect bond pads, wherein the via extensions bond to the bondpads by solder.
 20. A chip package as in claim 19 wherein the bondedarea of the via extensions to the bond pads are constricted.
 21. A chippackage as in claim 19 wherein only the top of the via extensions bondto the bond pads with a solder.
 22. A chip package as in claim 19wherein the top and a portion of the sides of the via extensions bond tothe bond pads with a solder.
 23. A chip package as in claim 19 whereinthe contactor bonds to a plurality of semiconductor chips.
 24. A chippackage as in claim 19 wherein the contactor bonds to semiconductorchips in a whole semiconductor wafer.